IS42S16400F
IC42S16400F
BURST READ/SINGLE WRITE
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccess
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occurs are defined below.
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀ
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bank m is registered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
while an access command with auto precharge enabled is
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tRP - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
33
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
