IS42S83200B, IS42S16160B
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A12
Input Pin
AddressInputs:A0-A12aresampledduringtheACTIVEcommand(row-addressA0-
A12)andREAD/WRITEcommand(columnaddressA0-A9(x8), orA0-A8(x16);with
A10 defining auto precharge) to select one location out of the memory array in the
respectivebank.A10issampledduringaPRECHARGEcommandtodetermineifall
banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The
addressinputsalsoprovidetheop-codeduringaLOADMODEREGISTERcommand.
BA0, BA1
CAS
Input Pin
Input Pin
Input Pin
BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE, READ, WRITEor
PRECHARGEcommandisbeingapplied.
CAS, inconjunctionwiththeRASand WE, formsthedevicecommand. Seethe
"CommandTruthTable"fordetailsondevicecommands.
CKE
TheCKEinputdetermineswhethertheCLKinputisenabled. Thenextrisingedgeofthe
CLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW. WhenCKEisLOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK
Input Pin
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
areacquiredinsynchronizationwiththerisingedgeofthispin.
CS
TheCSinputdetermineswhethercommandinputisenabledwithinthedevice.
Command input is enabled whenCSisLOW, anddisabledwithCSisHIGH. Thedevice
remains in the previous state when CS is HIGH.
DQML,
DQMH
Input Pin
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQMLandDQMHcontroltheoutputbuffer. WhenDQMLorDQMHisLOW, the
correspondingbufferbyteisenabled, andwhenHIGH, disabled. Theoutputsgotothe
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds toOE
inconventionalDRAMs.Inwritemode,DQMLandDQMHcontroltheinputbuffer.When
DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot
bewrittentothedevice.ForIS42S16160Bonly.
DQM
Input Pin
For IS42S83200B only.
DQ0-DQ7 or
DQ0-DQ15
Input/Output
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS
Input Pin
Input Pin
RAS,inconjunctionwithCASandWE,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
WE
WE,inconjunctionwithRASandCAS,formsthedevicecommand.Seethe"Command
TruthTable"itemfordetailsondevicecommands.
VDDQ
VDD
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
VDDQ istheoutputbufferpowersupply.
VDD isthedeviceinternalpowersupply.
VSSQ istheoutputbufferground.
VSSQ
VSS
VSS isthedeviceinternalground.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
