IS42S83200B, IS42S16160B
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
t
CK
t
CL
t
CH
CLK
CKE
tCKS
tCKH
t
CKS
t
CKS
tCMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/DQML
DQMH
A0-A9, A11, A12
A10
ROW
ROW
ALL BANKS
SINGLE BANK
t
AS
t
AH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08