IS42S16100E, IC42S16100E
Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
tCKS
t
CL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
BANK 1
ROW
t
t
AS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
BANK 0
tCH
t
CS
tQMD
DQM
DQ
tAC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
HZ
t
RCD
RAS
t
RCD
t
CAC
tRQL
t
t
RAS
RC
t
RP
t
RC
t
<
PRE>
<
ACT>
<ACT
>
<READ>
Undefined
Don't Care
CAS latency = 2, burstlength = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com
41
Rev. C
01/22/08