IC41C82052S
IC41LV82052S
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Min. Max.
-60
Min. Max.
Symbol
Parameter
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
15
ns
tOEH
OE Hold Time from WE during
READ-MODI&Y-WRITE cycle(18)
8
10
ns
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
0
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODI&Y-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODI&Y-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
32
47
25
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
56
100K
30
60
68
100K
35
ns
ns
ns
tPRWC
EDO Page Mode READ-WRITE
Cycle Time
tCOH
tOꢀꢀ
Data Output Hold after CAS LOW
5
0
12
5
0
15
ns
ns
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
tWHZ
tCSR
tCHR
tORD
Output Disable Delay from WE
CAS Setup Time (CBR RE&RESH)(20, 25)
CAS Hold Time (CBR RE&RESH)( 21, 25)
3
5
8
0
10
3
5
10
ns
ns
ns
ns
10
0
OE Setup Time prior to RAS during
HIDDEN RE&RESH Cycle
tREꢀ
tREꢀ
tT
Auto Refresh Period
2,048 Cycles
50
32
128
1
50
32
128
ns
ms
ms
Self Refresh Period
2,048 Cycles
1
Transition Time (Rise or &all)(2, 3)
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p& (Vcc = 5.0V + 10%)
One TTL Load and 50 p& (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
7
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
