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IC41LV44004-50JI 参数 Datasheet PDF下载

IC41LV44004-50JI图片预览
型号: IC41LV44004-50JI
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 4MX4, 50ns, CMOS, PDSO24,]
分类和应用: 动态存储器光电二极管
文件页数/大小: 20 页 / 196 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C4400x and IC41LV4400x Series  
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)  
(Recommended Operating Conditions unless otherwise noted.)  
-50  
Min. Max.  
-60  
Min. Max.  
Symbol  
Parameter  
Units  
tACH  
Column-Address Setup Time to CAS  
Precharge during WRITE Cycle  
15  
15  
ns  
tOEH  
OE Hold Time from WE during  
8
10  
ns  
READ-MODIFY-WRITE cycle(18)  
tDS  
Data-In Setup Time(15, 22)  
Data-In Hold Time(15, 22)  
0
8
0
ns  
ns  
ns  
ns  
tDH  
10  
tRWC  
tRWD  
READ-MODIFY-WRITE Cycle Time  
108  
64  
133  
77  
RAS to WE Delay Time during  
READ-MODIFY-WRITE Cycle(14)  
tCWD  
tAWD  
tPC  
CAS to WE Delay Time(14, 20)  
26  
39  
20  
32  
47  
25  
ns  
ns  
ns  
Column-Address to WE Delay Time(14)  
EDO Page Mode READ or WRITE  
Cycle Time  
tRASP  
tCPA  
RAS Pulse Width in EDO Page Mode  
Access Time from CAS Precharge(15)  
EDO Page Mode READ-WRITE  
Cycle Time  
50  
56  
100K  
30  
60  
68  
100K  
35  
ns  
ns  
ns  
tPRWC  
tCOH  
tOFF  
Data Output Hold after CAS LOW  
5
0
12  
5
0
15  
ns  
ns  
Output Buffer Turn-Off Delay from  
(13,15,19, 24)  
CAS or RAS  
tWHZ  
tCSR  
tCHR  
tORD  
Output Disable Delay from WE  
3
5
8
0
10  
3
5
10  
ns  
ns  
ns  
ns  
CAS Setup Time (CBR REFRESH)(20, 25)  
CAS Hold Time (CBR REFRESH)( 21, 25)  
OE Setup Time prior to RAS during  
HIDDEN REFRESH Cycle  
10  
0
tREF  
tT  
Auto Refresh Period  
2,048 Cycles  
4,096 Cycles  
1
32  
64  
1
32  
64  
ms  
ns  
Transition Time (Rise or Fall)(2, 3)  
50  
50  
AC TEST CONDITIONS  
Output load:  
Two TTL Loads and 50 pF  
Input timing reference levels: VIH = 2.4V, VIL = 0.8V  
Output timing reference levels: VOH = 2.0V, VOL = 0.8V  
8
Integrated Circuit Solution Inc.  
DR007-0B 10/17/2002