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IC41LV16256-60KG 参数 Datasheet PDF下载

IC41LV16256-60KG图片预览
型号: IC41LV16256-60KG
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, SOJ-40]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 21 页 / 209 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C16256  
IC41LV16256  
ELECTRICAL CHARACTERISTICS(1)  
(Recommended Operating Conditions unless otherwise noted.)  
Symbol Parameter  
TestCondition  
Speed Min.  
Max.  
Unit  
IIL  
Input Leakage Current  
Any input 0V < VIN < Vcc  
–10  
10  
µA  
Other inputs not under test = 0V  
IIO  
Output Leakage Current  
Output is disabled (Hi-Z)  
0V < VOUT < Vcc  
–10  
10  
µA  
VOH  
VOL  
ICC1  
Output High Voltage Level  
Output Low Voltage Level  
Standby Current: TTL  
IOH = –2.5 mA  
IOL =+2.1mA  
2.4  
V
V
0.4  
RAS, LCAS, UCAS > VIH Commerical 5V  
Industrial 5V  
2
3
1
2
mA  
Commerical 3.3V  
Industrial  
RAS, LCAS, UCAS > VCC – 0.2V  
3.3V  
ICC2  
ICC3  
Standby Current: CMOS  
5V  
1
mA  
mA  
3.3V  
0.5  
Operating Current:  
RAS, LCAS, UCAS,  
-25  
-35  
-50  
-60  
260  
230  
180  
170  
Random Read/Write(2,3,4)  
Average Power Supply Current  
Address Cycling, tRC = tRC (min.)  
ICC4  
ICC5  
ICC6  
Operating Current:  
RAS = VIL, LCAS, UCAS,  
-25  
-35  
-50  
-60  
250  
220  
170  
160  
mA  
mA  
mA  
EDO Page Mode(2,3,4)  
Cycling tPC = tPC (min.)  
Average Power Supply Current  
Refresh Current:  
RAS Cycling, LCAS, UCAS > VIH  
-25  
-35  
-50  
-60  
260  
230  
180  
170  
RAS-Only(2,3)  
tRC = tRC (min.)  
Average Power Supply Current  
Refresh Current:  
RAS, LCAS, UCAS Cycling  
-25  
-35  
-50  
-60  
260  
230  
180  
170  
CBR(2,3,5)  
tRC = tRC (min.)  
Average Power Supply Current  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each EDO page cycle.  
5. Enables on-chip refresh and address counters.  
Integrated Circuit Solution Inc.  
7
DR018-0C 04/23/2004