IC41C16105S
IC41LV16105S
CBR REꢀRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RP
t
RAS
t
RP
t
RAS
RAS
t
CHR
tCHR
t
RPC
CP
tRPC
t
t
CSR
tCSR
UCAS/LCAS
I/O
Open
HIDDEN REꢀRESH CYCLE(1) (WE = HIGH; OE = LOW)
t
RAS
t
RAS
t
RP
RAS
t
CRP
t
RCD
t
RSH
tCHR
UCAS/LCAS
t
AR
t
RAD
t
RAL
t
ASR
t
RAH
tCAH
t
ASC
ADDRESS
Row
Column
t
AA
t
RAC
(2)
OFF
t
t
CAC
t
CLZ
Open
Open
Valid Data
I/O
OE
t
OE
tOD
t
ORD
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOꢀꢀ is referenced from rising edge of RAS or CAS, whichever occurs last.
16
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001