IC41C16105
IC41LV16105
TRUTH TABLE
.unction
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word (Early Write)
Write: Lower Byte (Early Write)
Write: Upper Byte (Early Write)
Read-Write
(1,2)
Hidden Refresh
RAS-Only
Refresh
CBR Refresh
(4)
RAS
H
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
LCAS UCAS
H
H
L
L
L
H
H
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
WE
X
H
H
H
L
L
L
H→L
H
L
X
X
OE
X
L
L
L
X
X
X
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
D
OUT
Lower Byte, D
OUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
OUT
D
IN
Lower Byte, D
IN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
Read
Write
(1,3)
(2)
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
LCAS
or
UCAS
active).
2. These READ cycles may also be BYTE READ cycles (either
LCAS
or
UCAS
active).
3. EARLY WRITE only.
4. At least one of the two
CAS
signals must be active (LCAS or
UCAS).
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
S2-3
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
