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IC41LV44052-50J 参数 Datasheet PDF下载

IC41LV44052-50J图片预览
型号: IC41LV44052-50J
PDF下载: 下载PDF文件 查看货源
内容描述: [Fast Page DRAM, 4MX4, 50ns, CMOS, PDSO24,]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 18 页 / 205 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C4405x and IC41LV4405x Series  
AC CHARACTERISTICS(1,2,3,4,5,6)  
(Recommended Operating Conditions unless otherwise noted.)  
-50  
-60  
Symbol  
Parameter  
Min. Max.  
Min. Max.  
Units  
tRC  
Random READ or WRITE Cycle Time  
84  
50  
13  
25  
10K  
104  
60  
15  
30  
10K  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(6, 7)  
tRAC  
tCAC  
tAA  
Access Time from RAS  
50  
30  
8
60  
40  
10  
9
(6, 8, 15)  
Access Time from CAS  
Access Time from Column-Address(6)  
RAS Pulse Width  
tRAS  
tRP  
RAS Precharge Time  
tCAS  
tCP  
CAS Pulse Width(23)  
10K  
10K  
CAS Precharge Time(9)  
CAS Hold Time (21)  
9
37  
45  
tCSH  
tRCD  
tASR  
tRAH  
tASC  
tCAH  
tAR  
38  
12  
0
40  
14  
0
RAS to CAS Delay Time(10, 20)  
Row-Address Setup Time  
Row-Address Hold Time  
Column-Address Setup Time(20)  
Column-Address Hold Time(20)  
8
10  
0
0
8
10  
40  
Column-Address Hold Time  
(referenced to RAS)  
30  
tRAD  
tRAL  
tRPC  
tRSH  
tRHCP  
tCLZ  
tCRP  
tOD  
RAS to Column-Address Delay Time(11)  
Column-Address to RAS Lead Time  
RAS to CAS Precharge Time  
RAS Hold Time  
10  
25  
5
25  
15  
12  
12  
30  
5
30  
15  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
10  
35  
0
RAS Hold Time from CAS Precharge  
CAS to Output in Low-Z(15, 24)  
CAS to RAS Precharge Time(21)  
Output Disable Time(19, 24)  
30  
0
5
5
3
3
tOE  
Output Enable Time(15, 16)  
12  
15  
tOED  
tOEHC  
tOEP  
tOES  
tRCS  
tRRH  
Output Enable Data Delay (Write)  
OE HIGH Hold Time from CAS HIGH  
OE HIGH Pulse Width  
5
5
10  
5
10  
5
OE LOW to CAS HIGH Setup Time  
Read Command Setup Time(17, 20)  
0
0
Read Command Hold Time  
0
0
(referenced to RAS)(12)  
tRCH  
Read Command Hold Time  
0
0
ns  
(referenced to CAS)(12, 17, 21)  
tWCH  
tWCR  
Write Command Hold Time(17)  
8
10  
50  
ns  
ns  
Write Command Hold Time  
40  
(referenced to RAS)(17)  
tWP  
Write Command Pulse Width(17)  
8
7
10  
7
ns  
ns  
ns  
ns  
ns  
ns  
tWPZ  
tRWL  
tCWL  
tWCS  
tDHR  
WE Pulse Widths to Disable Outputs  
Write Command to RAS Lead Time(17)  
Write Command to CAS Lead Time(17, 21)  
Write Command Setup Time(14, 17, 20)  
Data-in Hold Time (referenced to RAS)  
13  
8
15  
10  
0
0
39  
39  
Integrated Circuit Solution Inc.  
DR013-0B 10/17/2002  
7