IS24C32A
IS24C64A/B
ISSI
Stop Condition
®
DEVICE OPERATION
IS24C32A/64A/64B features serial communication and
supports a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by a
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C32A/64A/64B is the Slave device on the bus.
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The
IS24C32A/64A/64B
contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line, which may cycle
the SCL up to nine times. (For each clock signal
transition to High, the Master checks for a High level on
SDA.)
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the data
line while the clock line is high will be interpreted as a
Start or Stop condition.
The state of the data line represents valid data after a Start
condition. The data line must be stable for the duration of the
High period of the clock signal. The data on the SDA line
may be changed during the Low period of the clock signal.
There is one clock pulse per bit of data. Each data transfer
is initiated with a Start condition and terminated with a Stop
condition.
Standby Mode
Power consumption is reduced in standby mode. The
IS24C32A/64A/64B will enter standby mode: a) At Power-
up, and remain in it until SCL or SDA toggles; b) Following
the Stop signal if a no write operation is initiated; or c)
Following any internal write operation.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
01/26/04
3
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
