IS24C32A
IS24C64A/B
FUNCTIONAL BLOCK DIAGRAM
ISSI
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
®
Vcc
8
SDA
5
WP
7
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
X
DECODER
SCL
6
CONTROL
LOGIC
EEPROM
ARRAY
Y
DECODER
GND
4
nMOS
ACK
Clock
DI/O
>
DATA
REGISTER
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
with the 24C16. When pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus
system. When the pins are not hardwired, the default values
of A0, A1, and A2 are zero.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus
requires
a pullup
resistor to Vcc.
WP
WP is the Write Protect pin. With IS24C32A/64A, if the WP
pin is tied to Vcc, the entire array becomes Write Protected
(Read only). With IS24C64B, if WP is tied to Vcc, the top
quarter of the array (1800h-1FFFh) becomes Write Protected.
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
01/26/04
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
