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AS7C3364PFD32B-166TQIN 参数 Datasheet PDF下载

AS7C3364PFD32B-166TQIN图片预览
型号: AS7C3364PFD32B-166TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 时钟静态存储器内存集成电路
文件页数/大小: 19 页 / 549 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C3364PFD32B  
AS7C3364PFD36B  
®
Functional description  
The AS7C3364PFD32B and AS7C3364PFD36B are high-performance CMOS 2-Mbit synchronous Static Random Access  
Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for  
highest frequency on any given technology.  
®
Timing for these devices is compatible with existing Pentium synchronous cache specifications. This architecture is suited  
™1  
for ASIC, DSP and PowerPC -based systems in computing, datacom, instrumentation, and telecommunications systems.  
Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t ) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus  
CD  
frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the  
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent  
internally generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip  
address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In  
a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are  
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock  
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next  
access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO  
®
input. With LBO unconnected or driven High, burst operations use a Pentium count sequence. With LBO driven LOW, the  
device uses a linear count sequence suitable for PowerPC and many other applications.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable  
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more  
bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).  
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are  
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled  
Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. This device operates in  
double-cycle deselect feature during read cycles.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC  
and ADSP are as follows:  
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.  
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).  
• Master chip enable CE0 blocks ADSP, but not ADSC.  
AS7C3364PFD32B and AS7C3364PFD36B family operates from a core 3.3V power supply. I/Os use a separate power supply  
that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.  
TQFP capacitance  
Parameter  
Symbol  
Test conditions  
VIN = 0V  
Min  
Max  
Unit  
pF  
*
Input capacitance  
CIN  
-
-
5
7
*
I/O capacitance  
CI/O  
VOUT = 0V  
pF  
* Guaranteed not tested  
TQFP thermal resistance  
Description  
Conditions  
Symbol  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
θJA  
θJA  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51  
22  
Thermal resistance  
θJC  
8
°C/W  
(junction to top of case)1  
1 This parameter is sampled  
1 PowerPCis a trademark International Business Machines Corporation.  
1/31/05; v.1.1  
Alliance Semiconductor  
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