AS7C3364NTD32B
AS7C3364NTD36B
®
AC test conditions
• Output Load: see Figure B,
except for t
, t
, t
, t
see Figure C.
LZC LZOE HZOE HZC
Thevenin equivalent:
• Input pulse level: VSS to 3V. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input rise and fall time (Measured at 0.3V and 2.7V): 1.0V/ns. See Figure A.
• Input and output timing reference levels: 1.5V.
319Ω / 1667Ω
Z0=50Ω
50Ω
DOUT
+3.0V
Dout
VL=1.5V
5 pF*
90%
10%
90%
10%
353Ω / 1538Ω
30 pF*
GND
*including scope
and jig capacitance
VSS
Figure C: Output load (B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
6
7
tCH measured as HIGH above VIH, and tCL measured as LOW below
VIL
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temper-
ature and voltage.
5
tHZCN is a ‘no load’ parameter to indicate exactly when SRAM outputs
have stopped driving.
4/28/05; v.1.3
Alliance Semiconductor
P. 15 of 19
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
