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AS7C3364FT36B-65TQI 参数 Datasheet PDF下载

AS7C3364FT36B-65TQI图片预览
型号: AS7C3364FT36B-65TQI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100]
分类和应用: 静态存储器
文件页数/大小: 19 页 / 417 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第6页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第7页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第8页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第9页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第11页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第12页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第13页浏览型号AS7C3364FT36B-65TQI的Datasheet PDF文件第14页  
AS7C3364FT32B  
AS7C3364FT36B  
®
Timing characteristics over operating range  
–65  
-75  
-80  
–10  
Notes  
1
Parameter  
Sym  
Min Max Min Max Min Max Min Max Unit  
Cycle time  
t
7.5  
6.5  
3.5  
8.5  
7.5  
3.5  
10  
8.0  
4.0  
12  
10  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CYC  
Clock access time  
t
CD  
Output enable LOW to data valid  
Clock HIGH to output Low Z  
Data output invalid from clock HIGH  
Output enable LOW to output Low Z  
Output enable HIGH to output High Z  
Clock HIGH to output High Z  
Output enable HIGH to invalid output  
Clock HIGH pulse width  
t
OE  
t
2.5  
2.5  
0
2.5  
2.5  
0
2.5  
2.5  
0
2.5  
2.5  
0
2,3,4  
2
LZC  
t
OH  
t
2,3,4  
2,3,4  
2,3,4  
LZOE  
HZOE  
t
3.0  
3.0  
3.5  
3.5  
4.0  
4.0  
5.0  
5.0  
t
HZC  
t
0
0
0
0
OHOE  
t
2.5  
2.5  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
3.0  
3.0  
2.0  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
0.5  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
4.0  
4.0  
2.0  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
0.5  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
4.0  
4.0  
2.0  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
0.5  
2.0  
2.0  
2.0  
0.5  
0.5  
0.5  
5
5
CH  
Clock LOW pulse width  
t
t
t
CL  
AS  
DS  
Address setup to clock HIGH  
Data setup to clock HIGH  
6
6
Write setup to clock HIGH  
t
6,7  
6,8  
6
WS  
Chip select setup to clock HIGH  
Address hold from clock HIGH  
Data hold from clock HIGH  
Write hold from clock HIGH  
Chip select hold from clock HIGH  
ADV setup to clock HIGH  
t
CSS  
t
AH  
DH  
WH  
t
6
t
6,7  
6,8  
6
t
CSH  
t
ADVS  
ADSP setup to clock HIGH  
ADSC setup to clock HIGH  
ADV hold from clock HIGH  
ADSP hold from clock HIGH  
ADSC hold from clock HIGH  
1 See “Notes” on page 16.  
t
6
ADSPS  
ADSCS  
t
6
t
6
ADVH  
ADSPH  
ADSCH  
t
6
t
6
Snooze Mode Electrical Characteristics  
Description  
Conditions  
Symbol  
Min  
Max  
Units  
Current during Snooze Mode  
ZZ active to input ignored  
ZZ > V  
I
30  
mA  
IH  
SB2  
PDS  
PUS  
t
t
2
2
cycle  
cycle  
cycle  
ZZ inactive to input sampled  
ZZ active to SNOOZE current  
ZZ inactive to exit SNOOZE current  
t
2
ZZI  
t
0
RZZI  
2/8/05; v.1.2  
Alliance Semiconductor  
P. 10 of 19