AS7C3364FT32B
AS7C3364FT36B
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
90%
10%
90%
10%
5 pF*
353Ω / 1538Ω
30 pF*
GND
*including scope
and jig capacitanc
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
,
BWE
,
BW[a:d].
CE2
Chip select refers to CE0
,
CE1
,
2/8/05; v.1.2
Alliance Semiconductor
P. 16 of 19
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
