AS7C33512PFS16A
AS7C33512PFS18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
D
L
OUT
5 pF*
90%
10%
90%
10%
for 3.3V I/O;
353Ω / 1538Ω
30 pF*
= V
/2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure C: Output load (B)
Figure A: Input waveform
Figure B: Output load (A)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
is less than t
and t
is less than t at any given temperature and voltage.
HZOE
LZOE
HZC
LZC
5) t measured HIGH above V and t measured as LOW below V
CH IH CL
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE, BWE, BW[a,b].
8) Chip select refers to CE0, CE1, CE2.
4/15/02; v.1.5
Alliance Semiconductor
12 of 14
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
