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Identification register definitions
Instruction field
512K x 18
xxxx
Description
Reserved for version number.
Revision number (31:28)
Device depth (27:23)
Device width (22:18)
Device ID (17:12)
00111
00011
xxxxxx
Defines the depth of 512K or 1Mb words.
Defines the width of x18, x32, or x36 bits.
Reserved for future use.
JEDEC ID code (11:1)
ID register presence indicator (0)
00000110100 Allows unique identification of SRAM vendor.
1
Indicates the presence of an ID register.
Scan register sizes
Register name
Instruction
Bypass
Bit size
3
1
ID
32
Boundary scan
x18:51
x36:70
Instruction codes
Instruction
Code
Description
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
EXTEST
000
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
IDCODE
001
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
SAMPLE Z
Reserved
010
011
Do not use. This instruction is reserved for future use.
Captures I/ O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
SAMPLE/ PRELOAD
100
Reserved
Reserved
101
110
Do not use. This instruction is reserved for future use.
Do not use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
111
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