AS7C33512NTD16A
AS7C33512NTD18A
®
Synchronous truth table
CE0
H
X
X
L
L
X
X
CE1
X
L
X
H
H
X
X
CE2
X
X
H
L
L
X
X
ADV/LD
L
L
L
L
L
H
X
R/W
X
X
X
H
L
X
X
BW[a,b]
X
X
X
X
L
X
1
X
OE
X
X
X
X
X
X
X
CEN
L
L
L
L
L
L
H
Address source
NA
NA
NA
External
External
Burst counter
Stall
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect, high-Z
Deselect, high-Z
Deselect, high-Z
Begin read
Begin write
Burst
2
Inhibit the CLK
1
Should be low for Burst write, unless a specific byte/s need/s to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = Low, H = High.
State Diagram for NTD SRAM
Burst
Read
Read
Read
Burst
Read
Dsel
Burst
Dse
l
Rea
d
Dsel
Dsel
Burst
ad
Re
W
rit
e
Read
Write
Write
Write
Write
ite
Wr
Burst
l
Dse
Burst
Write
Dsel
Burst
Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply
voltage
2.5V I/O supply
voltage
Address and
control pins
I/O pins
Ambient operating temperature
Symbol
V
DD
V
SS
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
IH
V
IL
V
IH
V
IL
T
A
Min
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.5
2
2.0
–0.5
2
0
Nominal
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
Max
3.6
0.0
3.6
0.0
2.65
0.0
V
DD
+ 0.3
0.8
V
DDQ
+ 0.3
0.8
70
Unit
V
V
V
V
V
°
C
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 V
IL
min = –2.0V for pulse width less than 0.2 × t
RC
.
3/11/02;
v.1.8H
Alliance Semiconductor
5 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
