AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
tADVH
tADVS
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
Read
Q(A1)
ADV
Burst
Write
Sus-
pend
Write
D(A1)
Suspend
Write
ADV
Burst
Write
Read
Q(A2)
ADV
Burst
Write
ADV
Burst
Write
Burst
Write
Suspend
Write
Write
3
D(A )
2
D(A )
3Ý01
2Ý01
D(A
)
D(A
)
2Ý01
D(A
)
3Ý10
2Ý10
2Ý11
D(A
)
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
12/1/04, v.1.2
Alliance Semiconductor
P. 13 of 20
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
