AS7C33256PFD32A
AS7C33256PFD36A
®
Timing characteristics for 3.3 V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol
Min Max Min Max Unit
Notes
f
–
166
–
–
133
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Cycle time
t
6
7.5
-
CYC
Clock access time
t
-
3.5
3.5
–
4.0
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
12/1/04, v.1.2
Alliance Semiconductor
P. 10 of 20
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
