AS7C33256NTF32A
AS7C33256NTF36A
®
AC test conditions
• Output Load: see Figure B,
Thevenin equivalent:
except for t
, t
, t
, t
see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
319
Ω
/1667
Ω
Z0=50Ω
50Ω
DOUT
+3.0V
Dout
VL=1.5V
5 pF*
GND
90%
10%
90%
10%
353Ω/1538
Ω
30 pF*
*including scope
and jig capacitance
GND
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1
2
3
4
5
6
7
8
9
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
tHZCN is a‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving.
ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
Transitions are measured ±500 mV from steady state voltage. Output loading specified with CL = 5 pF as in Figure C.
CH measured as high above VIH, and tCL measured as low below VIL
t
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs mus
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
11/8/04, v. 1.1
Alliance Semiconductor
P. 15 of 18
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
