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AS7C331MPFD36A-200TQI 参数 Datasheet PDF下载

AS7C331MPFD36A-200TQI图片预览
型号: AS7C331MPFD36A-200TQI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 1MX36, 3.1ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100]
分类和应用: 静态存储器
文件页数/大小: 19 页 / 525 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C331MPFD32A  
AS7C331MPFD36A  
®
Functional description  
The AS7C331MPFD32A/36A is a high-performance CMOS 32-Mbit Synchronous Static Random Access Memory (SRAM)  
device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any  
given technology.  
Fast cycle times of 5/6/7.5 ns with clock access times (t ) of 3.1/3.5/3.8 ns enable 200,166and 133MHz bus frequencies.  
CD  
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller  
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally  
generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip  
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In  
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are  
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock  
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next  
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input.  
With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device  
uses a linear count sequence.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable  
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more  
bytes may be written by asserting BWE and the appropriate individual byte BWn signals.  
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are  
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.  
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in double-  
cycle deselect feature during read cycles.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC  
and ADSP follow.  
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).  
Master chip enable CE0 blocks ADSP, but not ADSC.  
The AS7C331MPFD32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can  
operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.  
TQFP capacitance  
Parameter  
Input capacitance  
I/O capacitance  
Symbol  
Test conditions  
VIN = 0V  
Min  
Max  
Unit  
pF  
*
CIN  
-
-
5
7
*
CI/O  
VOUT = 0V  
pF  
* Guaranteed not tested  
TQFP thermal resistance  
Description  
Conditions  
Symbol  
θJA  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA/JESD51  
θJA  
22  
Thermal resistance  
(junction to top of case)1  
θJC  
8
°C/W  
1 This parameter is sampled  
2/10/05, v.1.1  
Alliance Semiconductor  
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