ꢀꢁꢂꢃꢄꢄꢅꢆꢇꢈꢉꢅꢊꢀ
&
Reserved
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.
TAP timing diagram
ꢙ
ꢖ
2
3
4
5
,ꢃꢄꢌꢐꢇ ꢝ!A
B,ꢇꢉC
ꢌ
ꢌ
ꢌ
,:,:
,:,ꢈ
,ꢈ,:
,ꢃꢄꢌꢐ#ꢝꢁꢃꢐ%ꢃ ꢃ!ꢌ
B,#%C
ꢌ ꢌ
#-,: ,:#;
,ꢃꢄꢌꢐꢅꢒꢌꢒ91ꢞ
B,ꢅ1C
ꢌ
,ꢈꢍ-
ꢌ
ꢌ
ꢅ-,:
,:ꢅ;
ꢌ
,ꢈꢍ;
,ꢃꢄꢌꢐꢅꢒꢌꢒ9ꢍꢎꢌ
B,ꢅꢍC
8ꢞꢁꢃ?ꢋꢞꢃꢁ
ꢅꢝꢞRꢌꢐ!ꢒꢂꢃ
TAP AC electrical characteristics
o
o
For notes 1 and 2, +10 C < T < +110 C and +2.4V < V < +2.6V.
J
DD
Description
Symbol
Min Max Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
tTHTH
fTF
tTHTL
tTLTH
100
ns
10 MHz
ns
40
40
ns
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
Setup Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
20
ns
ns
ns
10
10
TMS setup
tMVTH
10
10
ns
ns
1
Capture setup
tCS
Hold Times
TMS hold
tTHMX
10
10
ns
ns
1
Capture hold
tCH
1 t and t refer to the setup and hold time requirements of latching data
CS CH
from the boundary scan register.
2
Test conditions are specified using the load in the figure TAP AC output
load equivalent.
ꢉꢗꢘꢙꢘꢙꢚꢘꢛꢉꢖꢔꢉꢚꢔꢜꢔꢜꢉꢊꢒꢖꢌꢍꢎꢏꢉꢝꢍ ꢁ
ꢀꢋꢋꢌꢍꢎꢏꢐꢑꢁꢐꢒꢌꢏꢓꢎꢔꢕꢏꢖꢓꢗ
!ꢔꢉꢗꢗꢉꢁ ꢉꢗꢜ
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
