ꢊꢐꢗꢀ##"$%&ꢞ"(ꢊ
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Synchronous truth table
CE0
H
CE1
X
CE2
X
ADV/ LD R/ W BW[a,b] OE
CEN Address source
CLK
Operation
L
L
L
L
L
H
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
NA
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Deselect, high-Z
L to H Begin read
X
L
X
NA
X
X
H
NA
L
H
L
External
External
Burst counter
Stall
L
H
L
L
Lto H Begin write
L to H Burst2
1
X
X
X
X
X
X
X
X
X
X
L to H Inhibit the CLK
1 Should be low for burst write, unless specific bytes need to be inhibited
2 Refer to state diagram below.
Key: X = Don’t Care, L = Low, H = High
State diagram for NTD SRAM
*ꢎꢂꢄꢌ
&ꢃꢒꢁ
*ꢎꢂꢄꢌ
&ꢃꢒꢁ
*ꢎꢂꢄꢌ
&ꢃꢒꢁ
&ꢃꢒꢁ
ꢅꢄꢃ
*ꢎꢂꢄꢌ
ꢅꢄꢃ
*ꢎꢂꢄꢌ
*ꢎꢂꢄꢌ
)ꢂꢋꢌꢃ
*ꢎꢂꢄꢌ
)ꢂꢋꢌꢃ
)ꢂꢋꢌꢃ
)ꢂꢋꢌꢃ
Recommended operating conditions
Parameter
Symbol
VDD
Min
3.135
0.0
Nominal
Max
Unit
3.3
0.0
3.3
0.0
2.5
0.0
–
3.465
0.0
Supply voltage
V
GND
VDDQ
GNDQ
VDDQ
GNDQ
2.375
0.0
3.465
0.0
3.3V I/ O supply voltage
2.5V I/ O supply voltage
V
V
2.35
0.0
2.65
0.0
V
2.0
–0.52
VDD + 0.3
0.7
Address and
IH
V
control pins
V
–
IL
Input voltages1
V
2.0
–
VDDQ + 0.3
0.7
IH
I/ O pins
V
V
-0.52
0
–
IL
Ambient operating temperature
TA
–
70
° C
1 Input voltage ranges apply to 3.3V I/ O operation. For 2.5V operation, contact factory for input specifications.
2 V min = –2.0V for pulse width less than 0.2 x t .
IL
RC
ꢉꢗꢘꢙꢙꢘꢚꢙꢛꢉꢖꢔꢚꢔꢜꢔꢗꢊꢒꢖꢌꢍꢎꢏꢝꢍ ꢁ
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
