ꢊꢐꢗꢀ##"$%&ꢞ"(ꢊ
&
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
ꢀꢁꢂꢃꢂꢄꢅꢄꢆꢂꢇꢈꢅꢃꢉꢊꢂꢄꢋꢌ
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
/ꢘ&ꢘ'ꢁꢞꢒꢊꢁꢘ&ꢘ'ꢁꢚ(ꢎ)
(/*&ꢃ'ꢁꢞꢒꢊꢁ*&ꢃ'ꢁꢚ(ꢎ
ꢀꢃꢅΩꢂꢃꢆꢆꢇ
Ω
ꢀꢌꢁꢂꢁꢃꢄΩ
50Ω
D
OUT
+ꢘ&ꢄ'
'ꢐꢁꢂꢁ!&ꢃ'
ꢅꢍꢎꢏ
ꢃꢁꢐꢆꢙ
$%ꢅ
#ꢄ"
#ꢄ"
!ꢄ"
ꢞꢒꢊꢁꢘ&ꢘ'ꢁꢚ(ꢎ)
ꢂꢁ'ꢀꢀꢆ(*
ꢀꢁꢀΩꢂꢃꢁꢀꢄ
Ω
ꢘꢄꢁꢐꢆꢙ
!ꢄ"
$%ꢅ
ꢙꢇꢛ,ꢑꢉꢔꢇꢛꢈꢁ-,ꢒꢐꢋꢁ
ꢓꢛꢔꢁ.ꢇꢈꢁ,ꢓꢐꢓ,ꢇꢏꢓꢛ,ꢋ
ꢞꢒꢊꢁ*&ꢃ'ꢁꢚ(ꢎ
ꢆꢇꢈꢉꢊꢋꢁꢖꢍꢁꢚꢛꢐꢉꢏꢁꢜꢓꢝꢋꢞꢒꢊ
ꢆꢇꢈꢉꢊꢋꢁꢌꢍꢁꢎꢉꢏꢐꢉꢏꢁꢑꢒꢓꢔꢁꢕꢖꢗ
ꢆꢇꢈꢉꢊꢋꢁ+ꢍꢁꢎꢉꢏꢐꢉꢏꢁꢑꢒꢓꢔꢕꢌꢗ
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
is less than t
and t
LZOE HZC
is less than t at any given temperature and voltage.
LZC
HZOE
5) t measured HIGH above V and t measured as LOW below V
CH IH CL IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/ W, BW[a,b].
8) Chip select refers to CE0, CE1, CE2.
ꢉꢗꢘꢙꢙꢘꢚꢙꢛꢉꢖꢔꢚꢔꢜꢔꢗꢊꢒꢖꢌꢍꢎꢏꢝꢍ ꢁ
ꢀꢋꢋꢌꢍꢎꢏꢐꢑꢁꢐꢒꢌꢏꢓꢎꢔꢕꢏꢖꢓꢗ
!ꢔꢉ"ꢗꢉꢁ ꢉ"ꢜ
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
