December 2004
®
AS7C33128FT18B
3.3V 128K
×
18 Flow Through Synchronous SRAM
Features
•
•
•
•
•
•
•
•
Organization: 131,072 words × 18 bits
Fast clock to data access: 6.5/7.5/8.0/10.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow through operation
Asynchronous output enable control
Economical 100-pin TQFP package
Individual byte write and Global write
Multiple chip enables for easy expansion
•
•
•
•
•
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[16:0]
CLK
CS
CLR
Burst logic
2
2
17
Q
D
CS
Address
register
CLK
128K × 18
Memory
array
17
18
18
17
15
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
Byte Write
registers
CLK
D
DQa
Q
Byte Write
registers
CLK
D
2
OE
Enable
register
Q
CE
CLK
Output
Buffers
Input
registers
CLK
ZZ
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ [a,b]
Selection guide
–65
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
7.5
6.5
250
120
30
-75
8.5
7.5
225
100
30
-80
10
8.0
200
90
30
-10
12
10.0
175
90
30
Units
ns
ns
mA
mA
mA
12/10/04; v.1.3
Alliance Semiconductor
P. 1 of 19
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