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AS7C25512NTD36A-133TQIN 参数 Datasheet PDF下载

AS7C25512NTD36A-133TQIN图片预览
型号: AS7C25512NTD36A-133TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [ZBT SRAM, 512KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 18 页 / 428 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C25512NTD32A/36A  
®
Timing characteristics over operating range  
166  
133  
1
Parameter  
Clock frequency  
Sym  
Min  
Max  
166  
Min  
Max  
133  
Unit  
MHz  
ns  
Notes  
F
MAX  
CYC  
CD  
Cycle time  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6
7.5  
Clock access time  
3.5  
3.5  
3.8  
3.8  
ns  
Output enable low to data valid  
Clock high to output low Z  
Data output invalid from clock high  
Output enable low to output low Z  
Output enable high to output high Z  
Clock high to output high Z  
Output enable high to invalid output  
Clock high pulse width  
ns  
OE  
0
0
ns  
2,3,4  
2
LZC  
OH  
1.5  
0
1.5  
0
ns  
ns  
2,3,4  
2,3,4  
2,3,4  
LZOE  
HZOE  
HZC  
OHOE  
CH  
3.5  
3.5  
3.8  
3.8  
ns  
ns  
0
0
ns  
2.4  
2.3  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
0.5  
1.5  
0.5  
2.4  
2.4  
1.5  
1.5  
1.5  
1.5  
0.5  
0.5  
0.5  
0.5  
1.5  
0.5  
1.5  
0.5  
ns  
5
Clock low pulse width  
ns  
5
CL  
Address and Control setup to clock high  
Data setup to clock high  
ns  
6
AS  
ns  
6
DS  
Write setup to clock high  
ns  
6, 7  
6, 8  
6
WS  
Chip select setup to clock high  
Address hold from clock high  
Data hold from clock high  
Write hold from clock high  
Chip select hold from clock high  
Clock enable setup to clock high  
Clock enable hold from clock high  
ADV setup to clock high  
ns  
CSS  
AH  
ns  
ns  
6
DH  
ns  
6, 7  
6, 8  
6
WH  
ns  
CSH  
CENS  
CENH  
ADVS  
ADVH  
ns  
ns  
6
ns  
6
ADV hold from clock high  
ns  
6
1 See “Notes” on page 15  
Snooze Mode Electrical Characteristics  
Description  
Conditions  
ZZ > V  
Symbol  
Min  
Max  
Units  
mA  
Current during Snooze Mode  
ZZ active to input ignored  
I
40  
IH  
SB2  
PDS  
PUS  
t
t
2
2
cycle  
cycle  
cycle  
cycle  
ZZ inactive to input sampled  
ZZ active to SNOOZE current  
ZZ inactive to exit SNOOZE current  
t
2
ZZI  
t
0
RZZI  
12/23/04, v 2.2  
Alliance Semiconductor  
P. 9 of 18