$6&17'$$
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
FT
TDO
TDI
TMS
TCK
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
O
I
I
O
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
SYNC
SYNC
SYNC
SYNC
ASYNC
-
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias (junction)
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.3
–0.3
–0.3
–
–
–65
–65
Max
+3.6
V
DD
+ 0.3
V
DDQ
+ 0.3
1.8
50
+150
+150
Unit
V
V
V
W
mA
o
o
C
C
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Y $GYDQFH ,QIR
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3 RI
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
