ꢀꢈ"#ꢏꢑꢑꢓꢏꢝ !ꢖꢏꢀꢗꢖꢘꢀ
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TAP AC test conditions
Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V
TAP AC output load equivalent
ꢗ1ꢛ&0
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing refer ence levels. . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage. . . . 1.25V
&ꢚΩ
/ꢅꢍ
ꢛꢚꢏ.
2ꢍ?&ꢚΩ
TAP DC electrical characteristics and operating conditions
o
o
(+10 C < T < +110 C and +2.4V < V < +2.6V unless otherwise noted)
J
DD
Description
Conditions
Symbol
Min
Max
VDD + 0.3
0.7
Units
V
Notes
1, 2
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
V
1.7
-0.3
-5.0
IH
V
IL
V
1, 2
0V ≤ V ≤ VDD
IL
5.0
µA
IN
I
Outputs disabled,
Output leakage current
ILO
-5.0
5.0
µA
0V ≤ V ≤ VDDQ(DQx)
IN
Output low voltage
Output low voltage
Output high voltage
Output high voltage
IOLC = 100µA
V
0.2
0.7
V
V
V
V
1
1
1
1
OL1
I
OLT = 2mA
IOHS = -100µA
OHT = -2mA
V
OL2
V
OH1
2.1
1.7
I
V
OH2
1. All voltage referenced to V (GND).
SS
t
2. Overshoot: V (AC) ≤ V + 1.5V for t ≤ KHKH/ 2
IH
DD
t
Undershoot:V (AC) ≥ -0.5 for t ≤ KHKH/ 2
IL
Power-up: V ≤ +2.6V and V ≤ 2.4V and V ≤ 1.4V for t ≤ 200ms
DDQ
IH
DD
During normal operation, V
must not exceed V . Control input signals (such as LD, R/ W, etc.) may not have pulsed widths less than
DD
DDQ
t
(Min) or operate at frequencies exceeding f (Max).
KHKL
KF
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
