欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS7C25512NTD36A-100BC 参数 Datasheet PDF下载

AS7C25512NTD36A-100BC图片预览
型号: AS7C25512NTD36A-100BC
PDF下载: 下载PDF文件 查看货源
内容描述: [ZBT SRAM, 512KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, BGA-119]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 2 页 / 50 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号AS7C25512NTD36A-100BC的Datasheet PDF文件第2页  
6HSWHPEHU 
$GYDQFH ,QIRUPDWLRQ
Š
$6&17'$
$6&17'$
9 . î  65$0 ZLWK 17'
TM
)HDWXUHV
• Organization: 524,288 words × 32 or 36 bits
• NTD
architecture for efficient bus operation
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3/3.4/4 ns
• Fast OE access time: 3/3.4/4 ns
• Fully synchronous operation
• “Flow-through” or “pipelined” mode
• Asynchronous output enable control
• Economical 100-pin TQFP package
• 119 BGA (7 x 17 Ball Grid Array package)
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• 2.5V I/O operation
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
/RJLF EORFN GLDJUDP
A[18:0]
19
D
3LQ DUUDQJHPHQW IRU 74)3 WRS YLHZ

Q
19
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
D
Q
19
DQPc, NC
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
FT
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Address
register
Burst logic
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
FT
LBO
ZZ
DQ [a:d]
36/32
Write delay
addr. registers
CLK
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CLK
Control
logic
CLK
CLK
512K x 32
SRAM
Array
TQFP 14 x 20mm
D
Data
Q
Input
Register
CLK
36/32
36/32
36/32
36/32
CLK
CEN
CLK
OE
Output
Register
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb, NC
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DQPa, NC
36/32
OE
DQ [a:d]
Note: Pins 1,30,51,80 are NC for ×32
6HOHFWLRQ JXLGH
-200
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
NTD
is a trademark of Alliance Semiconductor Corporation.
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
 Y
$OOLDQFH 6HPLFRQGXFWRU
Write Buffer
-166
6
166
3.4
230
70
30
-100
10
100
4.0
150
50
30
Units
ns
MHz
ns
mA
mA
mA
5
200
3.0
280
100
30
3  RI 
&RS\ULJKW ‹ $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG