AS7C252MPFD18A
®
Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
A3
tAH
tAS
A1
A2
Address
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
t
OE
tCD
tHZC
tHZOE
tOH
tLZOE
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A1)
Dout
Read Suspend Read
Burst
Read
Burst
Read
Suspend
Read
2Ý10
Burst
Read
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL*
Q(A1)
2Ý01
2Ý10
2Ý11
Q(A
) Q(A
) Q(A
) Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
2/11/05, v.1.1
Alliance Semiconductor
10 of 18
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
