IS66WVC2M16ALL
Advanced Information
Burst Write Operation
After CE# goes LOW, the address to access is latched on the rising edge of the next clock
that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation
is going to be a WRITE (WE# =LOW, Figure 3).
Data is placed to the data bus (DQ0~DQ15) with consecutive clock cycles when WAIT de-asserts.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data
is to be transferred into (or out of ) the memory. WAIT will again be asserted at the
boundary of a row, unless wrapping within the burst length.
A full 4 word synchronous write access is shown in Figure 3 and the AC characteristics are specified in
Table 18.
Figure 3. Synchronous Write Access Timing
tCLK
CLK
VALID
ADDRESS
Address
tSP
tHD
tSP
tHD
DQ0-
DQ15
DATA IN
DATA IN
DATA IN
DATA IN
tAS
tAS
ADV#
tHD
tCSP
tCEM
CE#
tCBPH
tSP tHD
tHD
UB#/LB#
tHD
tSP
WE#
tCEW
tKHTL
HiZ
WAIT
Write Burst Identified (WE#=LOW)
10
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Rev.00B | March 2010
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