IS66WVC2M16ALL
Advanced Information
Low-Power Feature
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operation, or when the address and control inputs remain static for an extended period
of time. This mode will continue until a change occurs to the address or control inputs.
Temperature-Compensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor that
automatically adjusts the refresh rate according to the operating temperature. The
device continually adjusts the refresh rate to match that temperature.
Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping
of these partitions can start at either the beginning or the end of the address map (see
Table 9). READ and WRITE operations to address ranges
receiving refresh will not be affected. Data stored in addresses not receiving refresh will
become corrupted. When re-enabling additional portions of the array, the new portions
are available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume. During this 150μs period, the current
consumption will be higher than the specified standby levels, but considerably lower
than the active current specification.
DPD can be enabled by writing to the RCR using CRE or the software access sequence;
DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays
LOW for at least 10us.
15
www.issi.com – SRAM@issi.com
Rev.00B | March 2010
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
