IS62WV5128ALL,
IS62WV5128BLL
ISSI
55 ns
Min.
Max.
55
45
45
0
0
40
25
0
—
5
—
—
—
—
—
—
—
—
20
—
70 ns
Min. Max.
70
60
60
0
0
50
30
0
—
5
—
—
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
CS1
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
WE
HIGH to Low-Z Output
t
WC
t
SCS1
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
V
DD
-0.2V/V
DD
-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1
Controlled,
OE
= HIGH or LOW)
t
WC
ADDRESS
t
SCS1
t
HA
CS1
t
AW
WE
t
SA
t
HZWE
t
PWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
SD
t
HD
DIN
DATA-IN VALID
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/30/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
