®
ISSI
IS61SP6464
TRUTH TABLE
OPERATION
ADDRESS
USED
CE3 CE2 CE3
CE2
CE ADSP ADSC ADV WRITE OE CLK
I/O
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
X
L
X
X
L
X
X
X
H
X
X
X
H
X
L
X
X
X
X
H
X
X
X
H
L
H
L
X
L
L
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H Dout
L-H High-Z
None
X
X
X
L
L
L
None
X
X
X
L
L
L
None
L
L
None
L
H
H
H
H
L
None
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
None
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
None
L
L
External
External
External
External
External
Next
L
X
X
L
L
L
L
L
H
X
L
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
Din
L
L
L
L
H
H
H
H
H
H
L
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
Next
L
Next
L
H
X
X
L
Next
L
L-H
L-H
Din
Din
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
H
L
H
X
X
L-H
L-H
Din
Din
L
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
