IS43/46DR83200A, IS43/46DR16160A
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The
address bits registered coincident with the Read or Write command are used to select the starting column location
(A0-A8 for x16) and (A0-A9 for x8) for the burst access and to determine if the auto precharge A10 command is to
be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
DMa - DMb
RDQS,
RDQS
Notes:
1. An:n = no. of address pins - 1
2. DQm: m = no. of data pins - 1
3. For x8 devices:
DMa - DMb = DM; DQSa - DQSb = DQS;
DQSa
-
DQSb
=
DQS;
RDQS,
RDQS
available only for x8
4. For x16 devices:
DMa - DMb = UDM, LDM; DQSa - DQSb = UDQS, LDQS;
DQSa
-
DQSb
=
UDQS, LDQS
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/16/2012
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
