IRU3007
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regula-
tor must meet for Vcore:
a) Vo=2.8V , Io=14.2A,
DVo=185mV, DIo=14.2A
b) Vo=2V , Io=14.2A,
DVo=140mV, DIo=14.2A
Also, the on-board 3.3V supply must be able to provide
10A load current and maintain less than
±5%
total out-
put voltage variation.
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
Vcore
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total
DVo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
ESR
[
100
= 7mV
14.2
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the IRU3007 is 5mV and if the total
DI,
the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level shift-
ing during the load transient eases the requirement for
the output capacitor ESR at the cost of load regulation.
One can show that the new ESR requirement eases up
by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without volt-
age level shifting must be 7mV then after level shifting
the new ESR will only need to be 8.5mV if the trace
resistance is 5mV (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs
[
2
3
(Vspec - 0.02
3
Vo -
DVo)
DI
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typical.
Selecting 6 of these capacitors in parallel has an ESR
of
≈
6mV which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
3.3V supply
For the 3.3V supply, since there is not a fast transient
requirement, 2 of the 1500mF capacitors is sufficient.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
Rev. 2.1
08/20/02
Where :
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
DVo
= Output ripple voltage
DI
= load current step
For example, assuming:
Vspec =
±140mV
=
±0.1V
for 2V output
Vo = 2V
DVo
= assume 10mV = 0.01V
DI
= 14.2A
Then the Rs is calculated to be:
Rs
≤
2
3
(0.140 - 0.02
3
2 - 0.01)
= 12.6mV
14.2
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mV, the power dissipated is:
Io
2
3Rs
= 14.2
2
312.6
= 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mV, then the power dissipated is about 1W,
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mV which translated to
≈
6
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