IRLML5103GPbF
140
120
-V
GS
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
iss
C
oss
= C
ds
+ C
gd
20
I
D
= -0.60A
V
DS
= -24V
V
DS
= -15V
16
C, Capacitance (pF)
100
C
oss
80
12
60
C
rss
40
8
4
20
0
1
10
100
A
0
0.0
FOR TEST CIRCUIT
SEE FIGURE 9
1.0
2.0
3.0
4.0
5.0
A
-V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
10
10
-I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
-I
D
, Drain Current (A)
T
J
= 150°C
1
100µs
1
T
J
= 25°C
1ms
0.1
0.4
0.6
0.8
1.0
1.2
V
GS
= 0V
1.4
A
1.6
0.1
1
T
A
= 25°C
T
J
= 150°C
Single Pulse
10
10ms
100
A
-V
SD
, Source-to-Drain Voltage (V)
-V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
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