X9111
bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
. The
R/W bit is used to set the device to either read or write
mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
V
(MSB)
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9
NV
MSB
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
BIT 8
NV
BIT 7
NV
BIT 6
NV
BIT 5
NV
BIT 4
NV
BIT 3
NV
BIT 2
NV
BIT 1
NV
BIT 0
NV
LSB
TABLE 3. IDENTIFICATION BYTE FORMAT
Device Type
Identifier
Internal Slave
Address
Read or
Write Bit
R/W
ID3
0
(MSB)
ID2
1
ID1
0
ID0
1
0
A1
A0
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
Instruction
Opcode
Register
Selection
I2
(MSB)
I1
I0
0
RB
RB
0
0
1
1
RA
0
1
0
1
RA
REGISTER
DR0
DR1
DR2
DR3
0
0
(LSB)
5
FN8159.4
September 15, 2006
INTERSIL [ INTERSIL CORPORATION ]
