Block Diagram
BOOT1
UGATE1
PHASE1
VCC_5V
LGATE1
PGND
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PGOOD
SD1
VIN
SGND
SD2
VCC
BOOT2
UGATE2
PHASE2
VCC
LGATE2
POR
PGND
ENABLE
0.8V REFERENCE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
UV
PGOOD
UV
PGOOD
3
GATE3
g
m
*V
E
+
V
E
+
-
FB3
ISL6443
1400kΩ
FB1
180kΩ
18.5pF
18.5pF
1400kΩ
-
16kΩ
-
OC1
OC2
PWM2
180kΩ
VSEN2
-
+
+ 0.8V
REF
ERROR AMP 1
PWM1
16kΩ
-
+
+
ERROR AMP 2
SOFT2
+
SS1
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
+
0.8V
REF
ISEN2
ISEN1
-
CURRENT
SAMPLE
-
CURRENT
SAMPLE
CURRENT
SAMPLE
+
+
CURRENT
SAMPLE
OCSET1
OCSET2
+
0.8V REFERENCE
0.8V REFERENCE
+
-
+
OC1
OC2
-
+
VIN
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
SYNC
VCC
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
FN9044.2
August 9, 2006
INTERSIL [ INTERSIL CORPORATION ]
