ICL7106, ICL7107, ICL7107S
a
a
b
f
g
e
d
c
b
c
f
g
e
d
c
e
d
a
b
f
g
c
a
b
7
SEGMENT
DECODE
TYPICAL SEGMENT OUTPUT
V+
0.5mA
TO
SEGMENT
8mA
DIGITAL GROUND
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
V+
CLOCK
÷4
1000’s
COUNTER
100’s
COUNTER
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
10’s
COUNTER
1’s
COUNTER
1
V+
LOGIC CONTROL
500Ω
27
DIGITAL
GROUND
37
TEST
†
†
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
40
OSC 1
OSC 2
39
OSC 3
38
FIGURE 8. ICL7107 DIGITAL SECTION
System Timing
Figure 9 shows the clocking arrangement used in the
ICL7106 and ICL7107. Two basic clocking arrangements
can be used:
1. Figure 9A. An external oscillator connected to pin 40.
2. Figure 9B. An R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference
de-integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33
1
/
3
kHz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
66
2
/
3
kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/second) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).
40
INTERNAL TO PART
÷
4
CLOCK
39
38
GND ICL7107
TEST ICL7106
FIGURE 9A.
INTERNAL TO PART
÷
4
CLOCK
40
39
R
38
C
RC OSCILLATOR
FIGURE 9B.
FIGURE 9. CLOCK CIRCUITS
9
FN3082.8
INTERSIL [ INTERSIL CORPORATION ]
