EL7640, EL7641, EL7642
Fault Sequencing
Over-Temperature Protection
The EL7640, EL7641 and EL7642 have an advanced fault
detection system which protects the IC from both adjacent
pin shorts during operation and shorts on the output
supplies. A high quality layout/design of the PCB, in respect
of grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme – especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point, the device will shut down.
The upper and lower trigger points are typically set to 130°C
and -90°C respectively.
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
V
-slice Circuit
ON
The V -slice circuit functions as a three way multiplexer,
ON
switching the voltage on COM between ground, DRN and
SRC, under control of the start-up sequence and the CTL
pin.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1K impedance. Once the start-up
sequence has completed (C
stabilizes at ~1.18V),
DELAY
2. Place V
and V bypass capacitors close to the pins.
COM moves to the voltage on DRN. One clock cycle later,
CTL is enabled and acts as a multiplexer control such that if
REF
DD
3. Reduce the loop with large AC amplitudes and fast slew
CTL = 0, COM = DRN, CTL = V , COM = SRC.
rate.
IN
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
Op Amps
The EL7640, EL7641 and EL7642 have 1, 3 and 5 amplifiers
respectively. The op amps are typically used to drive the
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
TFT-LCD backplane (V
) or the gamma-correction
COM
divider string. They feature rail-to-rail input and output
capability, they are unity gain stable, and have low power
consumption (typical 600µA per amplifier). The EL7640,
EL7641 and EL7642 have a –3dB bandwidth of 12MHz while
maintaining a 10V/µs slew rate.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
Short Circuit Current Limit
The EL7640, EL7641 and EL7642 will limit the short circuit
current to ±180mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted for a
long time, the junction temperature will trigger the Over
Temperature Protection limit and hence the part will shut
down.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R1, R11,
Driving Capacitive Loads
EL7640, EL7641 and EL7642 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the –3dB bandwidth of the device will decrease and the
peaking will increase. The amplifiers drive 10pF loads in
parallel with 10kΩ with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output. However, this
will obviously reduce the gain. Another method of reducing
peaking is to add a “snubber” circuit at the output. A snubber
is a shunt load consisting of a resistor in series with a
capacitor. Values of 150Ω and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current and reduce the gain.
R41) and the V
REF
capacitor, C22, the C
capacitor
DELAY
C7 and the integrator capacitor C23.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
FN7415.1
17
September 26, 2005
INTERSIL [ Intersil ]
