DG444, DG445
Test Circuits and Waveforms
(Continued)
+15V
C
V+
V
S
IN
X
IMPEDANCE
ANALYZER
V
D
f = 1MHz
0V, 2.4V
GND
V-
-15V
C
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Application Information
FET INPUT
OP AMP 3
2
+5V
12
2
GAIN
1
A
V
= 1
GAIN
2
A
V
= 10
GAIN
3
A
V
= 20
GAIN
4
A
V
= 100
1
15
16
10
9
7
8
DG444 OR DG445
V-
GND
4
-15V
5
6
R
4
1kΩ
11
R
3
4kΩ
14
GND V-
R
2
5kΩ
V
L
+15V
+
7
V
IN
-
6
4
+15V
-15V
13
V+
3
V
OUT
+5V
V
L
+15V
+5V
+15V
V+
+15V
V
OUT
10kΩ
1
/ DG444
4
R
1
90kΩ
0V
0V
V
IN
FIGURE 7. LEVEL SHIFTER
GAIN ERROR IS DETERMINED ONLY BY
THE RESISTOR TOLERANCE, OP AMP OFFSET
AND CMRR WILL LIMIT ACCURACY OF CIRCUIT
R
1
+
R
2
+
R
3
+
R
4
V
OUT
--------------- = ------------------------------------------------ =
100
-
-
R
4
V
IN
WITH SW
4
CLOSED
FIGURE 6. PRECISION WEIGHTED RESISTOR
PROGRAMMABLE GAIN AMPLIFIER
6
FN3586.10
June 4, 2007
INTERSIL [ INTERSIL CORPORATION ]
