DG444, DG445
Test Circuits and Waveforms
V
O
is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
3V
LOGIC
INPUT
50%
0V
t
OFF
SWITCH
INPUT V
S
V
O
SWITCH
OUTPUT
0V
t
ON
80%
80%
LOGIC
INPUT
3V
t
r
< 20ns
t
f
< 20ns
SWITCH
INPUT
S
1
IN
1
R
L
GND
V-
C
L
V
L
V+
D
1
V
O
NOTE: Logic input waveform is inverted for switches that have
the opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications. C
L
includes fixture and
stray capacitance.
R
L
-
V
O
=
V
S
-----------------------------------
R
L
+
r
DS
(
ON
)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
SWITCH
OUTPUT
ΔV
O
V
L
R
G
V+
D
1
V
O
IN
X
(DG444)
OFF
ON
OFF
V
G
V-
C
L
IN
X
(DG445)
OFF
ON
Q =
ΔV
O
x C
L
V
IN
= 3V
OFF
GND
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
+15V
C
V+
+15V
SIGNAL
GENERATOR 10dBm
V
S
V
D
50Ω
SIGNAL
GENERATOR 10dBm
V
S
0V, 2.4V
IN
1
IN
2
0V, 2.4V
V
D
R
L
IN
X
0V, 2.4V
ANALYZER
R
L
V
D
C
GND
V-
-15V
NC
ANALYZER
GND
V-
C
-15V
FIGURE 3. CROSSTALK TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
5
FN3586.10
June 4, 2007
INTERSIL [ INTERSIL CORPORATION ]
