82C55A
Functional Description
I/O
PA7-
PA0
+5V
GND
GROUP A
PORT A
(8)
POWER
SUPPLIES
Data Bus Buffer
GROUP A
CONTROL
This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.
I/O
PC7-
PC4
GROUP A
PORT C
UPPER
(4)
BI-DIRECTIONAL
DATA BUS
I/O
DATA
PC3-
PC0
BUS
BUFFER
GROUP B
PORT C
LOWER
(4)
D7-D0
8-BIT
INTERNAL
DATA BUS
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
I/O
PB7-
PB0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
A0
RESET
(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.
CS
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
Group A and Group B Controls
82C55A BASIC OPERATION
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con-
trol word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that ini-
tializes the functional configuration of the 82C55A.
INPUT OPERATION
A1
0
A0
0
RD WR CS
(READ)
Port A → Data Bus
Port B → Data Bus
Port C → Data Bus
Control Word → Data Bus
0
0
0
0
1
1
1
1
0
0
0
0
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
0
1
1
0
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
1
1
OUTPUT OPERATION
(WRITE)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus → Port A
Data Bus → Port B
Data Bus → Port C
Data Bus → Control
DISABLE FUNCTION
Data Bus → Three-State
Data Bus → Three-State
X
X
X
X
X
1
X
1
1
0
3
INTERSIL [ Intersil ]
