AD7533
2. Monitor V
OUT
for a -V
REF
(1 - 1/2
10
) reading.
3. To increase V
OUT
, connect a series resistor, R2, (0Ω to
250Ω) in the I
OUT1
amplifier feedback loop.
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the V
REF
terminal.
A “Logic 1” input at any digital input forces the
corresponding ladder switch to steer the bit current to
I
OUT1
bus. A “Logic 0” input forces the bit current to I
OUT2
bus. For any code the I
OUT1
and I
OUT2
bus currents are
complements of one another. The current amplifier at
I
OUT2
changes the polarity of I
OUT2
current and the
transconductance amplifier at I
OUT1
output sums the two
currents. This configuration doubles the output range. The
difference current resulting at zero offset binary code,
(MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by
using an external resistor, (10MΩ), from V
REF
to I
OUT2
.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7533 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values, 4-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
±10V
+15V
V
REF
R1
MSB
4
DATA
INPUTS
LSB
R6 10MΩ
CR2
AD7533
13
3
15
14
16
1
2
R2
R
FEEDBACK
I
OUT1
I
OUT2
R4 5K
R3 5K
CR1
6
+
-
V
OUT
-
6
+
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
Offset Adjustment
TABLE 2. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB
1111111111
(NOTE 2)
NOMINAL ANALOG OUTPUT
511
-
-V REF
---------
512
1
-
-V REF
---------
512
0
1
-
+V REF
---------
512
511
-
+V REF
---------
512
512
-
+V REF
---------
512
1000000001
1000000000
0111111111
0000000001
5. Adjust V
REF
to approximately +10V.
6. Connect all digital inputs to “Logic 1”.
7. Adjust I
OUT2
amplifier offset adjust trimpot for 0V
±1mV
at
I
OUT2
amplifier output.
8. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.
9. Adjust I
OUT1
amplifier offset adjust trimpot for 0V
±1mV
at
V
OUT
.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor V
OUT
for a -V
REF
(1 - 2
-9
) volts reading.
3. To increase V
OUT
, connect a series resistor (R2) of up to
250Ω between V
OUT
and R
FEEDBACK
.
4. To decrease V
OUT
, connect a series resistor (R1) of up to
250Ω between the reference voltage and the V
REF
terminal.
0000000000
NOTES:
12. V
OUT
as shown in Figure 3.
13. Nominal Full Scale for the circuit of Figure 3 is given by:
1023
-
FSR
=
V REF
------------
.
512
14. Nominal LSB magnitude for the circuit of Figure 3 is given by:
1
-
LSB
=
V REF
---------
.
512
5
INTERSIL [ INTERSIL CORPORATION ]
