AD7523, AD7533
Detailed Description
The AD7523 and AD7533 are monolithic multiplying D/A
converters. A highly stable thin film R-2R resistor ladder
network and NMOS SPDT switches form the basis of the
converter circuit, CMOS level shifters permit low power
TTL/CMOS compatible operation. An external voltage or
current reference and an operational amplifier are all that is
required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the
ladder leg currents between I
OUT1
and I
OUT2
buses which
must be held at ground potential. This configuration main-
tains a constant current in each ladder leg independent of
the input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the out-
puts. Use of high threshold switches reduce offset (leakage)
errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first,
see Figure 1. This configuration results in TTL/CMOS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binarily weighted for an ON resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors and high accurate leg currents.
MSB
DATA
INPUTS
LSB
±10V
+15V
V
REF
14 R
FEEDBACK
4
16
AD7523/ 1 OUT1
AD7533
CR1
OUT2
11
3
2
15
GND
R2
-
6
+
V
OUT
NOTES:
1. R1 and R2 used only if gain adjustment is required.
2. CF1 protects AD7523 and AD7533 against negative transients.
FIGURE 2. UNIPOLAR BINARY OPERATION
TABLE 1. UNlPOLAR BINARY CODE - AD7523
DIGITAL INPUT
MSB LSB
11111111
ANALOG OUTPUT
255
-
–
V REF
---------
256
129
-
–
V REF
---------
256
V REF
128
-
–
V REF
---------
= – ----------------
-
256
2
127
-
–
V REF
---------
256
1
-
–
V REF
---------
256
0
-
–
V REF
---------
=
0
256
10000001
10000000
01111111
V+
1 3
4
6
TO LADDER
00000001
00000000
NOTE:
1. 1 LSB
=
(
2
–
8
8
9
TTL/
CMOS INPUT
1
-
) (
V
REF
)
=
---------
(
V
REF
)
.
256
2
5
7
I
OUT2
I
OUT1
Zero Offset Adjustment
1. Connect all digital inputs to GND.
FIGURE 1. CMOS SWITCH
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V
±1mV
(Max) at V
OUT
.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor V
OUT
for a -V
REF
(1
1
/
28
) reading.
3. To increase V
OUT
, connect a series resistor, R2, (0Ω to
250Ω) in the I
OUT1
amplifier feedback loop.
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the V
REF
terminal.
Typical Applications
Unipolar Binary Operation - AD7523 (8-Bit DAC)
The circuit configuration for operating the AD7523 in
unipolar mode is shown in Figure 2. With positive and
negative V
REF
values the circuit is capable of 2-Quadrant
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1.
10-11
INTERSIL [ INTERSIL CORPORATION ]
