ISL70001SRH
Pin Configuration
ISL70001SRH
(48 LD CQFP)
TOP VIEW
PGND1
PGND1
PGND2
PGND2
PVIN1
PVIN1
PVIN2
PVIN2
PVIN3
SYNC
LX1
LX2
6
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
31
18
19 20 21 22 23 24 25 26 27 28 29 30
PORSEL
AVDD
REF
LX6
PGND6
PGND6
PGND5
Pin Descriptions
PIN NUMBER
1, 2, 27, 28, 29, 30,
37, 38, 39, 40, 47,
48
3, 26, 31, 36, 41,
46
PIN NAME
PGNDx
DESCRIPTION
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The
Schottky diode should be located as close as possible to the IC.
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC.
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the
SYNC input of another ISL70001SRH. When configured as an input (Slave Mode), this pin accepts the SYNC
output from another ISL70001SRH or an external clock. Synchronization of the slave unit is 180° out-of-phase
with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the
frequency must be within the range of 1MHz ±20%.
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output
(Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE.
LXx
4, 5, 24, 25, 32, 33,
34, 35, 42, 43, 44,
45
6
PVINx
SYNC
7
8
9
10
11
M/S
ZAP
TDI
TDO
PGOOD
3
PGND5
PVIN6
PVIN6
FB
EN
FN6947.1
May 23, 2011
INTERSIL [ INTERSIL CORPORATION ]
