HS-81C55RH, HS-81C56RH
Waveforms
(Continued)
BASIC INPUT
tRP
RD
tPR
INPUT
BASIC INPUT
RD
tWP
INPUT
DATA BUS
DATA BUS
TIMER OUTPUT COUNTDOWN FROM 5 TO 1
LOAD COUNTER CLR
2
1
tF
5
4
t2
3
RELOAD COUNTER CLR
2
1
5
TIMER IN
tR
TIMER OUT
(PULSE)
(NOTE 1)
tTL
TIMER OUT
(SQUARE WAVE)
(NOTE 1)
tTL
NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE (M, MODE BIT = 1)
tTH
tTH
t1
tCYC
Functional Description
The HS-81C55RH and 81C56RH contains the following:
• 2K Bit Static RAM Organized as 256 x 8
• Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port
(PC)
• 14-Bit Timer-Counter
The IO/M (IO/Memory Select) pin selects either the five
register (Command, Status, PA0 - PA7, PB0 - PB7, PC0 -
PC5) or the memory (RAM) portion.
The 8-bit address on the Address/Data lines, Chip Enable
input CE or CE and IO/M are all latched on-chip at the falling
edge of ALE.
8-BIT INTERNAL DATA BUS
COMMAND
STATUS
PC
PB
PA
TIMER
MSB
TIMER
LSB
6
8
8
TIMER MODE
FIGURE 1. INTERNAL REGISTERS
6
INTERSIL [ INTERSIL CORPORATION ]
